In a previous posting we outlined the use of a FIFO between the Bitcoin engine (SHA256(SHA256(x))) and the communication circuit.
There have been a number of discussions about the futility of this implementation, along with the posting of various quantities of ‘dubious’ facts used by a number of people to backup the claim of why a FIFO is an exercise in futility.(a little thought into the actual statements, shows a massive & glaring mistake, that shows the same level of ineptitude as the greek governments ability to understand their current situation)
One key fact in my usage of a FIFO was to separate the Clock circuits of the communication & generation logic, failure to perform this, results in the need to continually adjust the counters used in the UART to match the master clock, this in-turn prevents the UART being “black-boxed”, because the UART needs to be continually re-routed in the logic, each time the clock frequency is changed, this in turn causes continual problems with the routing resources producing “random” results.
To date the 220MH/s core with the integral FIFO has been performing admirably, so what we are now going to do , is replace the handwritten FIFO VHDL with an integral core that is hardware specific to the virtex5.
It turns out that those clever people over at Xilinx added extra circuitry to the RAMB32 infrastructure to handle FIFO implementation in the RAM logic, even more interestingly, the FIFO is capable of operating at up to 550Mhz.
Since we are not actually using all the integral ram inside the Virtex 5, it is about time we replaced our generic VHDL FIFO with this infrastructure. At the very least it is additional logic that will no longer need to be routed to the same extent as it currently is, the only down side is that the minimum sized FIFO we can implement is 512 levels deep….., rather than our current 16 levels in the generic FIFO.
Let’s dooooo it!!
We can simulate this modification to death, but that is really not going to give us any insight into the actual results once it is implemented in the logic.
The first task will be to implement a single clock FIFO to replace the generic implementation.
After that, we will implement a dual clocked version with dual port ram, this will allow us to separate the clocks for the nonce communication & generation circuits, and if that works then we might start looking at inserting a FIFO BETWEEN the SHA256 generators, again it might be possible to use this to ‘break up’ the logic and increase the speed at which the SHA256 calculations can be operated.