Since the ASIC order went tits up at Tom’s ASIC fuckfest and BFL STILL have not delivered product, we spent the time working on our existing FPGA miner.
Improved in every way
Xilinx development boards are actually very good and it is a testament to the design of the Power-supplies that we managed to push the Bitcoin mining design to 200MH/s ,But why was the board consuming 47W when hashing hit 200MH/s?
The secondary issue was why the logic would not go faster than 200MH/s, even with improved FIFO & UART communication routines, try as we might I would not work, I had pushed the same FPGA to 250MHZ for another project, so it was unlikely to be clock related.
A new Beginning
It now seems that all these issues have now been solved after designing a completely new Power supply with improved layout (we also added two MASSIVE power planes which also act as a heat sink).
The FPGA design is now consuming 10W-15W per board and we have pushed the core to 370MH/s… yep a single core doing 370Mh/s….
So where is the power going?
0v95 Supply is sitting at about 6-7 Amps!!!
3v3 Supply is consuming about 1 amp, but that can be reduced since we have about 16 diagnostic LED’s strung off the IOAUX power line.
We may need to try and parallel up a couple of the 0v95 supplies in an attempt to cool the switching FETS down, we could just change the Capacitor/Inductor fet configuration, but that can be a real pain to get working efficiently, far easier to just parallel up a couple of supplies.
What is the point with ASICS being released soon?
Yep in good old hacker style, we may have discovered a weakness in the Litecoin system that would allow us to mine without consuming massive amounts of ram.
We say ‘might’ because we have only looked at the system very superficially, but if we are correct then with a minor performance hit we could limit down the ram size.