A couple of days ago I posted a screen shot of the Ebay Scrap miner pushing 120MH/s
All screenshots are taken after a reset job against the miner, so as the true rate can be seen
And each miner has produced 0% Invalids within the last 24 hours.
An “invalid” is when the FPGA hits an internal bit flip, producing a hash which it claims is valid but when checked is actually a bad hash.
Generally “invalids” are a good sign that something is not right with the FPGA/PSU or HDL bit file.
A good way to produce lots of invalids is to over-clock the FPGA or take it beyond a safe core temperature.
FOR-A bitminer (formally Ebay scrap job 11)
Since this board range has been modified into a viable miner, it has been given a formal name.
The required RS232 connections are as follows:
Please keep in mind that these connections are tied into the FPGA relative to about 2.5v-3.3v
Therefore you MUST implement an FTDI level convertor FT232RL is fine.
By purchasing the correct breakout boards, the I/O can be configured at 3V3 5V0 or with the use of the VIO pin on the FTDI device , you can configure non-standard voltages.
The markings in the photograph are relative to the FPGA so TX is TX OUT, RX is RX in.
When connecting to the FTDI chip you make the connection:
TX(FPGA) to RX(FTDI)
RX(FPGA) to TX(FTDI)
Poor product design
As pointed out in part one, FOR-A product design is poor on a number of levels.
First Issue, they do not bring all the FPGA pins through the PCB, instead terminating some on the top layer others are terminated halfway through the board, but everything that appears on the underside of the PCB is in use and also offset strangely.
Possibly done to confuse reverse-engineer probes (it might also be the reason for their abysmal attempt at disabling the JTAG with EXTERNAL logic!!!)
Failure to bring all the FPGA pads through the board means that any re-flow profile will be completely to cock…., because many of the pins are trapped under the FPGA, but do not appear on the bottom layer, so cannot get enough heat to re-flow correctly….
Then we have the ‘stupidity’ of massive ground planes on the bottom of the P.C.B COVERING the FPGA pins on earlier levels..
this results in you having to use an unsuitable re-flow profile to get the bloody FPGA to solder.. which in turn weakens the other pins that DO come through the board.
**(If any one has actually taken a VIRTEX FPGA apart… (mee.meee.meee), you will see something very strange, the metal ‘top’ is actually a massive airspace, with a very small chip area bang in the centre of this top, in effect the ONLY way to transfer heat from the top cap is through the die area of the FPGA.
so if you need to solder the BGA pins without heat from the bottom you need to get the FPGA up-to about 400 Deg.c… for 8 minutes.
Then there is the issue related to PCB flex and only soldering the FPGA to the top layer… since the pin pads have a massive FPGA to hold in place, they pads pull out of the top layer!!!.
Ultimately we had to sacrifice a PCB to discover the FPGA connections.
Power supply design
In this area, a simple WTF will suffice……
They use BOTH the PCI Express 12V & 3V3, they then take the 12V and regulate it down to 5V(+-3%), then use a TDK 5v to 5v regulator for accuracy!!! this feeds various other DC/DC convertors.. all very expensive Japanese kit. (Japanese love to promote their own industries at the customers cost)
The 3V3 is then badly regulated(+-3%) to 1V5 and fed to further DC/DC regulators.
The whole thing is then strung together like a set of christmas tree lights with various systems to ‘prevent’ incorrect power-up.
With a reasonable amount of stupidity thrown in…..
I.E If you turn off the 3V3 line then the board powers down (correctly) to protect various aspects of the circuit.
BUT….. if you DISCONNECT the 3V3 to simulate an open condition, then 90% of the board powers up and then attempts to burn out various DC/DC section and other components…
You can hear the DC/DC convertors whining and in some cases the ceramic caps physically breaking over!!!
(next time guys connect a pulldown/pull up to the 3V3 line to cover this floating situation!!!)
Also DUMP your current PSU design , go Texas Instruments & MAXIM and save 50% of the cost…
So it is within this complete abortion of a power supply system that we will attempt to combine all the input voltage connections to be 12V.
Really we should just pull off the whole 12v DC/DC shit and run 5V DC into the supplies, but removing the DC/DC bricks is going to be too difficult for most people.
Combining the Power Supplies
The PCB WILL NOT be suitable for insertion into a PCI slot after this modification….,but we will ensure the mod can be ‘backed out’ if needed.
The Two main DC/DC convertors we are interested in are the Bellnix BST04 (3V3) and the BST12(5V5)
After checking the spec sheets we can see that the BST04 can be safely driven from 5V5 (you can see where we are going with this!!)
We see that pin 2 is the input voltage and pin 5 is the output regulated supply.
First off we check to ensure that the PCI 3V3 is ONLY connected to the BST04,
next job is to link the BST12 output to the BST04 input, effectively eradicating ALL the 3V3 supply and driving it off the 12V.
The 12V BST12 is ‘rated’ at 16A which would give us 6A for each FPGA with 2A for the other DC/DC convertors and 2A headroom…
Currently the BST12 consumes 1A4 and the BST04 5A5 when the PCB is configured with firmware.