One major issue with generating bitcoins is getting rid of the heat from the crypto hashing engines. This is partially due to poor design of many of the crypto engines, or the incessant need of miners to over-clock the rigs until the errors are in double figures….
However many Bitcoin miners do not take into account the ambient temperature when designing their cooling solutions( and some cooling solutions are just CRAP… blue flashing lights anyone?, radioactive coolant?…. but ..but. is green and it glows in the dark…yep… chicks just dig flashy lights and green coolant.)
Currently the outside temperature in Hong Kong is about 31 degrees out of the sun. (whhooo), last-night with outside venting of heat, the temperature in the miners room was an astounding 39 Degrees, one issue is that ‘houses’ in Hong Kong are built out of a F*** massive SINGLE block of concrete WITHOUT cooling breaks or linings.(and they wonder why they crack….)
So basically you have a massive solar absorption unit during the day… which re-radiates the heat during the night(it also radiates cool in winter and can get damned cold…).
Therefore any cooling solution needs to be able to operate in excess of 40 Degrees, but still ensure the crypto engines do not hit melt down temperature…
Unless you are a bit-coiner North of the boarder who can steal their electricity or someone who has silently hidden away a rig in a factory…..
Whilst Designing the FPGA cores, I ensured that they were capable of measuring both the internal core voltages and the die temperature, unfortunately many (all) of the Ebay Scrap I have so far purchased goes to extensive lengths to defeat the internal Xilinx monitoring systems(What is the point in a manufacturer providing monitoring tools if stupid engineers are doing their utmost to disable them.)
Xilinx system Monitor
System Monitor is a hardwired FPGA core that is supplied on the silicon of most top of the line Xilinx products, you can disable it (either physically or via bit file configuration), doing so is fine, but the core is still there sitting in the middle of the FPGA.
Unfortunately many PCB designers INSIST on physically disabling the core externally (you can achieve this by tying the VDD pins to ground, Xilinx have a REALLY helpful hint…
don’t tie the VDD pins to GND if they are still connected to VDD….)
So you would think that the PCB engineers would have a 0R link to the system monitor pin with the option to link the resistor over to the supply rails (just incase they would need it for diagnostics.)….
Noooooo that would be far to easy….. Instead they use the shitty method of tying the VDD pin to GND in their schematics.. Which on a Via’d multilayer PCB connects the pin to each and every GND plane on the multilayered PCB, if you are lucky it is one GND plane, unfortunately some multilayer PCB can go as high as 4,6,8 ground planes.
The result… to all intents and purposes is you cannot re-enable the system monitors core logic without trying to cut through each and every one of these layers, which quite frankly is impossible without CNC controlled drills and would leave the final layer bonded to the FPGA pin very thin and fragile.
The only other option would be to drill out the section of the PCB and try to solder down the resulting hole directly to the BGA ball….
Well that was less of a success than I had hoped, luckily we only damaged the PCB and none of the internal interconnects, so after the experiment we could pop the PCB back into the mining rig.
Just need to figure out why I have an urge to drink milk…..